A data communication network may have different communication links with different capacity and other characteristics interconnected by switching nodes. Data may be grouped together into individual packets for delivery over various links between an origination node and a destination node. Each packet may include payload data along with control information, such as routing and error control. A complete communication session between origination and destination nodes may involve the transfer of any number of packets in a packet stream. The origination node and any number of intermediate nodes route the packets which make up the packet stream to the intended destination.
In some networks the physical route traversed by packets may change over the course of a communication session. In these and other situations, either a gap may appear in the packet stream flowing through a switching node, multiple packets may arrive at the switching node simultaneously, or a gap may be preceded or followed by multiple packets. This irregular packet stream flow poses problems when the route over which packets depart a network switching node includes a communication link operated at or near its maximum capacity because excess capacity is unavailable to handle the multiple packet situation.
First-in-first-out (FIFO) buffer memories may be included upstream from communication links operated at or near maximum capacity to temporarily store packets, smooth any irregular packet stream flow, and permit the communication links to efficiently operate at or near maximum capacity. Unfortunately, the use of conventional FIFO buffer memories is not a satisfactory solution when the switching node drives many parallel output channels each of which may operate at or near its maximum capacity. Implementing numerous conventional independent FIFO buffers for numerous channels is particularly inefficient. For example, a large number of gates is required to implement a single FIFO buffer in a conventional application specific integrated circuit (ASIC). When this large number is multiplied by the number of bits per packet, by the number of packets which need to be buffered, and by the number of channels which are operated in parallel, the resulting number of gates is exorbitant because it increases power, physical space, and expense requirements to undesirably high levels while diminishing reliability.